1. Field of the Invention
The present invention relates to a digital-to-analog converter converting a digital signal into an analog signal, and more particularly to a digitalto-analog converter for digital-to-analog conversions by applying different gate voltages to plural metal oxide semiconductor (MOS) transistors having the same operating characteristics.
2. Description of the Related Art
The digital-to-analog converter is a device for converting a digital signal into an analog signal. The digital-to-analog converter is used in diverse electronic chips. Equation 1, below, defines electric currents output from the digital-to-analog converter.Io=Iref*(b0*20+b1*21+b2*22+b3*b3+ . . . +bn−1*2n−1)
In Equation 1, above, Io denotes an output current of a digital-to-analog converter, bn denotes a bit value of 0 or 1, and Iref denotes a reference level. In detail and for example, if a digital signal of 1100 has been input, an output current, Io, of the digital-to-analog converter can be calculated as Iref(0*1+0*1+1*4+1*8)=12*Iref.
In order to output such current as calculated using Equation 1, the digital-to-analog converter uses plural current sources each supplying current of 2n, respectively. A current source can use an MOS transistor biased by a predetermined bias signal. Further, the current output from the MOS transistor can be expressed in Equation 2 as below.
                    I        =                                            μ              *              C                        2                    *                      W            L                    *                                    (                                                V                  gs                                -                                  V                  t                                            )                        2                                              [                  Equation          ⁢                                          ⁢          2                ]            
In Equation 2, μ denotes electron mobility in an MOS channel, C denotes capacitance per unit area of a parallel plate capacitor formed by a gate electrode and the channel, W denotes width of the gate electrode, L denotes length of the gate electrode, Vgs denotes a potential difference between the gate and the source, and Vt denotes a threshold voltage. In view of Equation 2, the magnitude of an output current can be changed depending on the width and length of the gate electrode and depending on a gate-source voltage.
FIG. 1 is a circuit diagram for showing a structure of a digital-to-analog converter disclosed in U.S. Pat. No. 6,577,260. In FIG. 1, the conventional digital-to-analog converter has a current source 10, a switch unit 20, and a clock feed-through removal switch 30.
The current source 10 is configured with plural current mirror circuits. Gates of TC and TC0 are connected to each other, so current I is output from the gate TC0, which has the same magnitude as current flowing in the gate TC. Further, different designs are applied to the width and lengths of the gate electrodes TC1 to TCn connected to the gate of TC0 in the same structure, which enables electric current output from a transistor to have the form of 2n*I in magnitude. Current output from the current source 10 results in I, 2I, 4I, 8I, . . . 2nIin magnitude.
The switch unit 20 has plural first switches TS0 to TSn connected to the transistors of the current source 10. The first switches TS0 to TSn are turned on or off depending on digital input signals D0 to Dn. A digital input signal can be a low-level pulse or a high-level pulse corresponding to an input binary code of 0 or 1. The high-level pulse causes the first switches to be turned on. Thus, the first switches turned on cause currents to flow from the transistors of the current source 10 to a next stage.
The clock feed-through removal switch 30 has plural second switches DT0 to DTn connected to the first switches TS0 to TSn of the switch unit 20. The MOS transistors are used as the first switches TS0 to TSn of the switch unit 20, and the first switches TS0 to TSn perform switching operations according to a certain input clock, which causes the feed-through due to electric charges accumulated in transistor channels. Such a feed-through caused by the accumulated charges can be eliminated with digital-inverting input signals applied to the second switches DT0 to DTn.
FIG. 2 is a view for describing drawbacks to the digital-to-analog converter of FIG. 1. In FIG. 2, a digital input signal is changed from “0111” to “1000”, further description of which will be made below. In Equation 1, analog current corresponding to “0111” is 7Iref in magnitude, and analog current corresponding to “1000” is 8Iref in magnitude.
The MOS transistors for the first switches TS0 to TSn have the same operating characteristics as the transistors TC0 to TCn in order to pass the currents output from the transistors TC0 to TCn of the current source 10 to a next stage. Thus, as a switch passes relatively large current, the load on the switch increases in proportion to the current, and the switch speed of the switch decreases in proportion to the current. Accordingly, as shown in FIG. 2, the switching speed changes in the order of D0, D1, D2, and D3, so that the switches D0 to D3 are turned on at times t1 to t4, respectively, as the digital input signal changes from “0111” to “1000”. Output current Io is identical to a sum of currents output from the switches, so that output current Io has a magnitude corresponding to 0110 in a time interval from t1 to t2, 0100 in a time interval from t2 to t3, and 0000 in a time interval from t3 to t4, but the output current Io reaches a magnitude corresponding to 1000 after the time point t4, which causes a problem of poor glitch characteristics since errors occur for the time interval from t1 to t4.
FIG. 3 is a circuit diagram for showing in brief a re-structured digital-to-analog converter disclosed in U.S. Pat. No. 5,969,658. The digital-to-analog converter in FIG. 3 is built with plural resistors connected. That is, plural first resistors each having the same resistance of R is arranged in series, and resistors each having resistance of 2R are connected to their connection nodes, respectively. Thus, a voltage Vref applied to one end of the first resistors is distributed across the first and second resistors. As a result, current such as I, (½)I, (¼)I, and (⅛)I can be output through the plural second resistors, respectively. Referring to FIG. 3, if switches (not shown) connected to the second resistors are controlled on and off according to a digital input signal, the digital-to-analog converter can output analog currents having a predetermined magnitude corresponding to the digital input signal.
However, if the switches are turned on, the switches each have turn-on resistance of a certain magnitude, which results in a problems of accurate digital-to-analog-converting operations since it is difficult to maintain a resistance ratio adjusted upon designs of the digital-to-analog converter.